1. Field of the Invention
The invention relates to a television receiver with a horizontal deflection circuit for cathode ray tube television receivers.
2. Description of the Related Art
FIG. 1 is a diagram of a control circuit 1 of a horizontal deflection circuit 2.
The deflection circuit consists mainly of a horizontal deflection yoke coil 3 connected in parallel with a retrace capacitor 4, a yoke-current damper diode 5 and a NPN bipolar transistor 6 acting as horizontal output device. The emitter of transistor 6 and the anode of diode 5 are connected to ground.
The collector of transistor 6 is connected to a supply voltage 7 through the primary winding 8 of a flyback transformer 9. The secondary high voltage winding 10 of the flyback transformer 9 generates voltage pulses (`horizontal flyback pulses`) supplying the cathode ray tube anode (not illustrated).
The base of transistor 6 is connected to an output of the integrated circuit 1 and is controlled by a horizontal deflection control signal referenced "Hdrive inverse".
The integrated circuit 1 synchronizes horizontal synchronization pulses in the video signal and the horizontal flyback pulses. It includes a comparator 11 comparing two signals, Vsaw and Vcomp. The former is derived from the horizontal synchronization pulses (through a signal referenced PHI2tb), while the latter is derived from the horizontal flyback pulses and the horizontal synchronization pulses (through a signal referenced PHI2ref).
PHI2ref is generated by a decoder from an n-bit counter which is reinitialised by the leading edge of a horizontal synchronization pulse in the video signal. The decoder is programmed so that the signal has a cyclic ratio of approximately 50%, but another ratio is possible.
PHI2tb is generated by a logic circuit which will be explained in more detail later on in relation with FIG. 6. It contains pulses of a frequency which is approximately the double of the line frequency.
A signal HFLYInt is generated from the horizontal flyback pulses by a hysteresis comparator 12, which generates a step signal for the duration of each flyback pulse. The use of hysteresis reduces the influence of noise.
The signals HFLYint and PHI2ref are compared by a phase comparator 13 to yield a control signal of a charge pump 14. The charge pump 14 charges or discharges a capacitor 15. The voltage on this capacitor is the signal Vcomp, which is fed to the negative input of comparator 11.
PHI2tb is fed to the `Set` input of an RS-latch 16. The output `Q inverse` of latch 16 controls the state of a switch 17. A current source 18 loads a capacitor 19 with a constant current. When closed, switch 17 connects the middle point between current source 18 and capacitor 19 to ground, unloading capacitor 19. The switch is open when Q inverse is set. The signal at this middle point is the signal Vsaw, which is fed to the positive input of comparator 11.
The middle point is also connected to the negative input of a comparator 20, which compares Vsaw to a constant voltage V. The output of this comparator 20 resets the RS-latch 16.
The output of Vsaw/Vcomp comparator 11 is fed to a control logic and reshape circuit 21, whose output is the signal Hdrive inverse driving the base of transistor 6. The function of the circuit 21 is, among other tasks, to transform its input signal into a step signal.
The operation of the control circuit 1 of FIG. 1 can be explained with the help of the diagrams of FIGS. 2 and 3.
FIG. 2 shows from top to bottom the control signal Hdrive of transistor 6, the current "I" in the deflection yoke and the flyback voltage "V fly back". Hdrive is inverted (Hdrive inverse) to control the base of NPN transistor 6. Interval A represents the line tracing interval, while interval B represents the horizontal blanking interval or flyback interval. During interval A, the yoke current I increases linearly. For negative values of I, the damper diode 5 conducts, while for positive values, the transistor 6 conducts. Interval C represents the signal on the base of the transistor. To allow proper current establishment, the active part (step C) of signal Hdrive is in advance on the instant at which the current I changes polarity. Interval D corresponds to the storage time of the transistor.
The horizontal synchronization pulses of a composite video baseband signal (CVBS) trigger the leading edge of a pulse in the signal PHI2ref, which should be in phase with the maximum of the horizontal flyback pulses as illustrated. The diagrams of FIG. 3 represent the signals when in-phase status is achieved.
Rising edges on PHI2tb trigger charging of capacitor 19 by current source 18. This is the constant positive slope X of the sawtooth of signal Vsaw. When Vsaw reaches the voltage level V, the RS-latch is reset, and switch 17 closed, which leads to a rapid drop to ground of the voltage stored in the capacitor 19. Follows a period during which the stored voltage remains at ground, until another rising edge on PHI2tb sets the RS-latch 16 anew.
Comparator 11 outputs a zero-to-one transition each time when Vsaw becomes greater than Vcomp. The first zerotoone transition triggers the active Hdrive step through circuit 21, while the second zero-to-one transition resets this signal to its inactive state. It can be seen immediately that the variation of the Vcomp comparison level will cause a phase change of the active Hdrive step.
The Vcomp signal is adjusted in the following manner. Charge pump 14 is active only during flyback pulses (existence of step pulse in HFLYint) and charges capacitor 15 starting from the leading edge of HFLYint, until the leading edge of PHI2ref. From that instant on until the end of the flyback pulse, capacitor is discharged. Charging and discharging currents have same intensity.
When the flyback pulse is centered on the leading edge of PHI2ref, the charging and discharging times are equal. Consequently, the voltage level of Vcomp before and after a pulse remains the same.
This is not true when the leading edge of PHI2ref is not in phase with the flyback pulse as described in the previous paragraph. When the pulse is in advance of PHI2ref, capacitor 15 will be charged a longer time: the Vcomp comparison level will increase, causing a delay of the Hdrive step (shift to the right on the diagram), thus retarding the flyback pulse. Conversely, the flyback pulse is advanced when the Vcomp comparison level is reduced.
Two sawteeth, X and Y, are shown on FIG. 4. The rising slope of sawtooth X is the same slope as on FIG. 3. Noise present on the slope induces a jitter on the triggering of the active Hdrive step, as illustrated. Due to the presence of noise, the Hdrive step may be triggered too early or to late.
The inventors have noted that a steeper slope X or Y will reduce the influence of noise on the jitter of the Hdrive signal, but that a steeper slope will also reduce the maximum amplitude of phase correction: it can be seen on FIG. 4 that the maximum correction Phi2 is greater than the maximum correction Phi1.